The manufacture of many types of work pieces requires the substantial planarization or polishing of at least one surface of the work piece. Examples of such work pieces that require a planar surface include semiconductor wafers, optical blanks, memory disks, and the like. Without loss of generality, but for ease of description and understanding, the following description of the invention will focus on applications to only one specific type of work piece, namely a semiconductor wafer. The invention, however, is not to be interpreted as being applicable only to semiconductor wafers. Those of skill in the art instead will recognize that the invention can be applied to any generally disk shaped work pieces.
One commonly used technique for planarizing the surface of a work piece is the chemical mechanical planarization (CMP) process. The terms “planarization” and “polishing,” or other forms of these words, although having different connotations, are often used interchangeably by those of skill in the art with the intended meaning conveyed by the context in which the term is used. For ease of description such common usage will be followed and the term “chemical mechanical planarization” will generally be used herein with that term and “CMP” conveying either “chemical mechanical planarization” or “chemical mechanical polishing.” In the CMP process a work piece, held by a work piece carrier head, is pressed against a polishing pad in the presence of a polishing slurry. The polishing pad is mounted on a platen and the work piece is moved relative to the polishing pad by placing the work piece and/or the platen in motion. The mechanical abrasion of the surface caused by the relative motion of the work piece with respect to the polishing pad combined with the chemical interaction of the slurry with the material on the work piece surface ideally produces a planar surface.
The conventional CMP process, for example as applied to a bulk silicon wafer, uses a two step, two platen process. The first platen is used for the primary polishing of the surface of the silicon wafer and the second platen is used to improve surface roughness, reduce haze, and to reduce the number of particulates remaining after the primary polish. The primary polishing is accomplished with a basic aqueous colloidal or fumed silica slurry and a porous polishing pad. The second process step on the second platen is intended to remove the majority of the residual slurry particles and surface damage remaining on the surface from the primary polish step. Typically different CMP parameters are used on the second platen including an alternative speed of relative motion between the wafer and the polishing pad, an alternative wafer pressure, extended rinse times, and the addition of surfactants to improve wettability of the wafer surface and to suppress the redeposition of particles on the wafer surface. The second process step is usually followed by a third step in which the wafer is transferred to a contact poly vinyl acetate (PVA) brush cleaning station at which the wafer is mechanically scrubbed and rinsed.
There are a number of inherent limitations in the present CMP process, especially as critical dimensions (CDs) of semiconductor devices manufactured on the silicon wafer decrease. As the CD decrease, so also does the size of “killer defects” defined as 50% of CD. Killer defects are those defects which have a high probability of causing malfunctioning of the semiconductor device. The first polishing step on the first platen leaves the surface of the silicon wafer hydrophobic. The hydrophobic surface allows particles to dry on the wafer surface during the wafer transfer from the first platen to the second platen. The particles that dry on the wafer surface chemically bond to that surface One of the accepted “rules” for post CMP cleaning (see, for example, Shin et al., Chemical Mechanical Polishing in Silicon Processing; Academic Press: New York, 2000; Vol. 63. 228-240ff, 183-213ff, 31-34ff.) is to never allow the polishing slurry to dry on the wafer surface. Allowing the wafer surface to dry greatly reduces the efficiency of cleaning the silicon to the extent that only re-polishing may be effective in removing the chemically bonded particles. Additionally, PVA brushes become less effective in removing particles as the particle size decreases because the area and mass of the particles decreases more rapidly than the adhesive forces keeping the particles on the silicon surface. Consequently the PVA brushes exert insufficient drag and lift on small particles, making the PVA brush cleaning technology ineffective. Further, in addition to being ineffective in removing small particles, the PVA brushes are consumables; the PVA material wears during the cleaning process and the material can be transferred to the silicon surface adding an additional contaminate to the surface. PVA brushes can also become loaded with both silicon particles and slurry particles as well as other CMP byproducts. These particles and byproducts can be transferred to subsequent otherwise clean wafers and can cause both contamination and micro scratches. To reduce the loading, the PVA brushes must be periodically flushed with, for example, with a diluted ammonium hydroxide solution. The process of flushing the brushes is time consuming. Supplying the flushing solution and replacing the consumable PVA brushes add to the cost of the overall CMP process.
Accordingly, it is desirable to provide a CMP process that yields a surface of the desired planarity without leaving contaminates on the work piece surface. In addition, it is desirable to provide a CMP process that yields the desired surface planarity at a lower cost and at a higher throughput and efficiency. Still further, it is desirable to provide a chemical mechanical cleaning (CMC) process, for the efficient cleaning of a work piece following chemical mechanical planarization of that work piece. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.